expandFMINIMUMNUM_FMAXIMUMNUM: Quiet is not needed for NaN vs NaN #139237
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@llvm/pr-subscribers-backend-amdgpu @llvm/pr-subscribers-llvm-selectiondag Author: YunQiang Su (wzssyqa) ChangesNew LangRef doesn't requires quieting for NaN vs NaN, aka the result may be sNaN for sNaN vs NaN. Full diff: https://github.com/llvm/llvm-project/pull/139237.diff 1 Files Affected:
diff --git a/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
index ba34c72156228..2c63c54fc03f7 100644
--- a/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
@@ -8683,11 +8683,6 @@ SDValue TargetLowering::expandFMINIMUMNUM_FMAXIMUMNUM(SDNode *Node,
SDValue MinMax =
DAG.getSelectCC(DL, LHS, RHS, LHS, RHS, IsMax ? ISD::SETGT : ISD::SETLT);
- // If MinMax is NaN, let's quiet it.
- if (!Flags.hasNoNaNs() && !DAG.isKnownNeverNaN(LHS) &&
- !DAG.isKnownNeverNaN(RHS)) {
- MinMax = DAG.getNode(ISD::FCANONICALIZE, DL, VT, MinMax, Flags);
- }
// Fixup signed zero behavior.
if (Options.NoSignedZerosFPMath || Flags.hasNoSignedZeros() ||
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Missing test changes |
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OK to merge? @arsenm |
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@arsenm ping |
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arsenm
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May 23, 2025
| ; GFX8-NEXT: s_movk_i32 s4, 0x8000 | ||
| ; GFX8-NEXT: v_lshrrev_b32_e32 v4, 16, v3 | ||
| ; GFX8-NEXT: v_cndmask_b32_e32 v3, v1, v0, vcc |
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I'm surprised how big the diff is here. I'm also surprised AMDGPU is going through this path for any type, bfloat should have promoted to float?
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I cannot find the code that set FMAXIMUMNUM/FMINIMUMNUM to promoted for BF16 for AMD64.
I guess that it is another bug.
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diff --git a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
index ade88a16193b..5e4bd36f96d0 100644
--- a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
+++ b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
@@ -213,7 +213,7 @@ SITargetLowering::SITargetLowering(const TargetMachine &TM,
ISD::FLOG10, ISD::FEXP, ISD::FEXP2, ISD::FEXP10,
ISD::FCEIL, ISD::FTRUNC, ISD::FRINT, ISD::FNEARBYINT,
ISD::FROUND, ISD::FROUNDEVEN, ISD::FFLOOR, ISD::FCANONICALIZE,
- ISD::SETCC}) {
+ ISD::SETCC, ISD::FMAXIMUMNUM,ISD::FMINIMUMNUM}) {
// FIXME: The promoted to type shouldn't need to be explicit
setOperationAction(Opc, MVT::bf16, Promote);
AddPromotedToType(Opc, MVT::bf16, MVT::f32);
@@ -776,6 +776,10 @@ SITargetLowering::SITargetLowering(const TargetMachine &TM,
Vec16, Custom);
setOperationAction(ISD::INSERT_VECTOR_ELT, Vec16, Expand);
}
+ for (MVT Vec16 :
+ {MVT::v2bf16, MVT::v4bf16, MVT::v8bf16, MVT::v16bf16, MVT::v32bf16}) {
+ setOperationAction({ISD::FMAXIMUMNUM, ISD::FMINIMUMNUM}, Vec16, Promote);
+ }
}
if (Subtarget->hasVOP3PInsts()) {
I have a try with this patch. It seems making some difference. Since I don't understand AMDGPU well, I don't know whether it is correct.
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We will use it to be sure that the canonicalize is removed in llvm#139237
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We will use it to be sure that the canonicalize is removed in #139237
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… (#141218) We will use it to be sure that the canonicalize is removed in llvm/llvm-project#139237
New LangRef doesn't requires quieting for NaN vs NaN, aka the result may be sNaN for sNaN vs NaN. See: llvm#139228
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New LangRef doesn't requires quieting for NaN vs NaN, aka the result may be sNaN for sNaN vs NaN.
See: #139228